Overview

The GW28-125 SerDes is a hard IP solution that delivers 125 Gbps of bi-directional throughput at ~ 1 pJ/bit across corners and is ideal for both ultra-short reach organic substrate on multi-chip-modules.

It achieves low power through a combination of carefully chosen coding, efficient circuitry, and simple clocking and equalization schemes.

Features

  • No interposer required.
  • Double-stackable.
  • High pin-efficiency, low power, and low fixed latency.
  • 86 Gbps/mm bidrectional data throughput.
  • Supports up to 3 dB channel insertion loss at 12.5 GHz.
  • NRZ-like inter-symbol interference (ISI) performation.
  • NRZ-like EMI, SSO and balance properties.

Applications

  • USR links inside a shared package.
  • Processor-to-SerDes chiplet links.
  • Processor-to-Optics chiplet links.
  • Switch-to-switch links.
  • Links between heteorgenous chiplets.

Deliverables

  • Datasheet and application notes
  • Standard integration views: GDSII, SDC, LEF, Verilog, .lib
  • Reference models and test benches
  • Test/characterization report (nominal silicon only)
  • Package design and integration guidelines
  • Testability and manufacturing guidelines
  • Evaluation modules
  • All documents available on request. Contact us for more details.

Specifications

Aspect Specifications
Technology Planar
Process Contact us for more details
Throughput 125 Gbps
Baud rate 25 Gbaud max
Bit error rate (across all corners) 1E-15 (native; without any FEC)
Insertion loss 3 dB
Power ~ 1 pJ/bit
Area 1.5 mm (die edge) x 0.4 mm (deep)
Bump pitch 150 µ
Beachfront BW/mm 83 Gbps bi-directional