The GW16-500 SerDes is a hard IP solution that delivers 500 Gbps of bi-directional throughput at ~ 1 pJ/bit across corners and is ideal for both ultra-short reach organic substrate on multi-chip-modules. It achieves low power through a combination of carefully chosen coding, efficient circuitry, and simple clocking and equalization schemes.


  • 2-4x throughput at > 50 % energy savings compared to conventional SerDes.
  • No interposer required
  • Double-stackable
  • High pin-efficiency, low power, and low fixed latency
  • 208 Gbps/mm (single stack)
  • Supports up to 6dB channel insertion loss at 12.5 GHz
  • NRZ-like inter-symbol interference (ISI) performance
  • NRZ-like EMI, SSO and balance properties
  • Can be double-stacked to double throughput per mm of die edge.


  • USR links inside a shared package.
  • Processor-to-SerDes chiplet links.
  • Processor-to-Optics chiplet links.
  • Switch-to-switch links.
  • Links between heteorgenous chiplets.


  • Datasheet and application notes
  • Standard integration views: GDSII, SDC, LEF, Verilog, .lib
  • Reference models and test benches
  • Qualification report
  • Package design and integration guidelines
  • Testability and manufacturing guidelines
  • Evaluation modules
  • All documents available on request. Contact us for more details.

GW16-500 Specifications



Technology FinFET
Process Various metal stacks available.
Contact us for more details
Throughput 500 Gbps
Baud rate 25 Gbaud max
Bit error rate
(across all corners)
1E-15 (native; without any FEC)
Insertion loss 6 dB
(across all corners)
~ 1 pJ/bit
Area 2.4 mm (die edge) x 1.0 mm (deep)
Bump pitch 150 µm
Beachfront BW/mm 208 Gbps bidi
Volume ship Q4 '18

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