Glasswing Interconnect Solutions
The GW-500 Quad Glasswing PHY is the first PHY to utilize Chord™ Signaling, an innovative new PHY technology. Glasswing uses CNRZ-5 Chord Signaling, a form of signaling that fits in the space between single-ended and differential signaling. Chord Signaling can make almost every interface better by getting more bits through with lower power and fewer pins without sacrificing margins.
GW-500 supports the following key features:
- 500 Gbit/s of bi-directional throughput
- 1.04 pJ/bit or 1 Tbit/s per watt
- Beachfront bandwidth: 208 Gbit/s/mm die edge
- 6dB insertion loss budget (40+ mm on GZ-41 substrate)
- Standard 150 μm bump pitch; NO interposer required!
- Low, fixed latency
- Native BER of 1E-15
- Optional Forward Error Correction (FEC) can be implemented to improve BER well below 1E-20
- PRBS pattern generators and loopback modes
- Protocol agnostic
- Built-in EyeScope and advanced diagnostics
Uses the Chord Signaling Code CNRZ-5
This code has inherently higher throughput per pin than equivalent NRZ solutions and inherently lower power per bit than equivalent PAM-4 solutions. The code allows Glasswing to get more bits through with less power.
Excellent Diagnostic Capabilities
The integrated EyeScope allows non-destructive testing of in-service links and test-equipment level debug of out-of-service links.
Supports Large MCMs
The 40+ mm reach and corner turning capability of the Glasswing allows MCMs up to 70mm to be efficiently supported. This allows a complex collection of dies to be integrated on a package substrate or organic interposer for a System in Package (SiP) solution.
Delivers Massive Bandwidth
Glasswing can be tiled in both directions to deliver terabits of bandwidth between dies.
- Divide your chip into multiple dies or chiplets
- Implement each portion of your solution in the most appropriate semiconductor process
- Avoid the use of difficult and costly silicon interposer technology in your product
- Reduce the size of your largest die in order to enhance its yield or address reticle size limits
- Create an ecosystem of interconnecting chiplets with common interfaces
- Tiling on CPUs, DSPs, or AI accelerator processors
- Separating the IO subsystem function on the Ethernet or OTN switch core
- Separating the radio interface from the processing subsystem in a high bandwidth 5G system
- Separating Analog to Digital Converters (ADCs) from a digital subsystem
- Separating a custom analog subsystem from a digital subsystem